1. Technical Field
The disclosure relates to a stacked-chip packaging structure and a fabrication method thereof.
2. Description of Related Art
In modern information era, consumers continuously pursue electronic products with high speed, outstanding quality, and multiple functions. The design of exterior appearances of the electronic products reveals a trend of light weight, thinness, small size, and compactness. In order to comply with the aforementioned trend, a multi-chip packaging module has been developed recently. In the multi-chip packaging module, a plurality of chips with identical or different functions are packaged together on a carrier. The carrier is a substrate or a lead frame, for example, and the carrier is electrically connected to external circuits through the carrier. Therefore, the multi-chip packaging module has a fast transmission speed, a short transmission path, and favorable electric characteristics, and a size of the multi-chip packaging structure and an area occupied thereby are further reduced. As a result, the multi-chip packaging technology has been extensively applied in a variety of electronic products and become the mainstream of future market.
In a stacked-chip packaging structure, the multi-chip packaging technology is adopted to stack a plurality of chips or a plurality of passive devices on the same carrier. FIG. 1A is a conventional cross-sectional view illustrating a stacked-chip packaging structure in which chips are connected by through holes and bumps. FIG. 1B is a diagram illustrating surface temperature distribution of the stacked-chip packaging structure shown in FIG. 1A. Referring to FIGS. 1A and 1B, conventionally, a plurality of chips 110 are stacked together and disposed on a substrate 120. The chips 110 can be electrically connected to one another through a plurality of through holes 140 and bumps 130 disposed among the chips 110.
Nonetheless, when heat is generated on certain area on the chips 110 during operation of the chips 110, the heat is mostly dissipated laterally through the chips 110. By contrast, it is relatively difficult to dissipate heat vertically through air and the bumps 130 among the chips 110, which results in large thermal resistance. Thereby, hot spots with high temperature are prone to be formed on the chips 110, and the overheated hot spots may cause damages to the chips 110 and generate thermal stresses at the bumps 130. As such, reliability of the stacked-chip packaging structure 100 is deteriorated.